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precisely what is a virtual clock: By definition, a virtual clock is often a clock with none supply. Stating extra evidently, a virtual clock is actually a clock which has been defined, but has not been associated with any pin/port. A virtual clock is applied being a reference to constrain the interface pins by relating the arrivals at input/output ports with respect to it with all the assistance of input and output delays.

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How you can outline a virtual clock: The simplest sdc command syntax to determine a virtual clock is as follows:create_clock -name VCLK -period ten .The above mentioned SDC command will determine a virtual clock “VCLK” with time period 10 ns.Goal of defining a virtual clock: The advantage of defining a digital clock is that we are able to specify sought after latency for virtual clock. As stated earlier mentioned, virtual clock is used to time interface paths. Determine one demonstrates a state of affairs in which it can help to determine a digital clock. Reg-A is flop inside block that is sending info by pORT outside the block.

Due to the fact, it is a synchronous signal, we are able to presume it for being captured by a flop (Reg-B) sitting exterior the block. Now, in the block, the trail to pORT is usually timed by specifying output hold off for this port with a clock synchronous to clock_in. We will specify a hold off with regard to clock_in alone, but there lies the problem of specifying the clock latency. If we specify the latency for clock_in, it'll be applied to Reg-A also. Applying output delay with regard to your authentic clock leads to input ports to get comfortable and output ports to get tightened following clock tree has become created. Allow us to elaborate it in some detail beneath. Let's suppose clock time period to generally be 10 ns and also the spending budget allotted to generally be 3 ns inside; thus, aquiring a "set_output_delay" of 7 ns.

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